Job Details

Familiar with Cadence tools Virtuoso and Xcelium. Fusion Compiler expertise a bonus.

SystemVerilog Real Number Modeling of analog circuitry (Behavioral)

AMS Co-Simulation and Verification

Verification of analog circuitry in analog domain

Verification of analog circuitry with automated SVRNM checkers.

Verification of behavioral models of analog circuitry in analog domain

Verification of behavioral models of analog circuitry with automated SVRNM checkers.

Command line simulation expertise preferred but not required.

Expertise in ITAG PDL/ICL preferred but not required.

Expertise in UVM preferred but not required.